Low Power Full Adder Using 9T Structure
In this paper, the authors propose a new 9T 1-bit full adder. The main objective is full output voltage swing, low power consumption and temperature sustainability. The proposed design is more reliable in terms of power consumption, Power Delay Product (PDP) and temperature sustainability as compared to the existing full adder designs. The design has been implemented 45nm technology on Tanner EDA tool version 13.0. The simulation results demonstrate the power consumption, delay and power delay product at different input voltages ranging 0.4V to 1.4V.