International Journal of Research in Advent Technology (IJRAT)
In this paper, the author presents as low power efficient full adder with minimized number of transistors. All the DSP processors consist of adder circuits. The power consumption in a full adder circuit is majorly due to EX-OR gates. In this paper, a novel EX-OR gate is proposed with only two transistors. This full adder utilizes only six transistors which consume 33.3% less power when compared to eight transistor full adder which was designed earlier. Simulation results were observed using MICROWIND tool.