Low Power Heterogeneous Adder

Provided by: WSEAS
Topic: Hardware
Format: PDF
Flexibility and portability has increased the requirement of low power components in fields like multimedia, signal processing and other computing applications. Adders are the essential computing elements in such applications. However the present adder architectures with hybrid/heterogeneous features provide performance variations but limits to consume less power. In this paper, low power heterogeneous adder architecture is proposed to enable flexibility to the computing applications and consume less power. 128 bit heterogeneous adder architecture is built using three low power sub-adders (ripple carry, carry look ahead and carry bypass adders).

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