Low Power High Performance SRAM Design Using VHDL

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Provided by: Global Journals
Topic: Hardware
Format: PDF
Data retention and leakage current are among the major area of concern in today's CMOS technology. In this paper 6T SRAM cell has been analyzed on the basis of Read Noise Margin (RNM), Write Noise Margin (WNM), read delay, write delay, and Data Retention Voltage (DRV). Implementation and simulation is carried out using VHDL. The word "Static" indicates that the memory retains its contents as long as power remains applied. SRAM indicates that locations in the memory can be accessed, i.e. written or since it is volatile memory and preserves data only while power is continuously applied.
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