Guru Jambheshwar University of Science & Technology
In this paper, the authors describe a new design of low power 3-2 compressor circuit for high speed multipliers. Power consumption of proposed 3-2 compressor circuit varies from 0.355 nW to 1.6964 nW and delay varies from 2.0390 ns to 2.0224 ns. Further, power delay product of proposed circuit varies from 7.23x10-18 (J) to 34.30x10-18 (J) with varying supply voltage from 1.8V to 3.3V. The proposed compressor circuit shows better performance in terms of power consumption, output delay and PDP as compared to previous reported 3-2 compressor circuits. Simulation has been carried out using 0.18-Î¼m CMOS technology.