Low Power Implementation and Analysis of Digital Fir Filter Based Low Power Multiplexer Base Shift/Add Multiplier
Conventional FIR filters consist of cells equal in number to the length of the filter i.e. the number of data taps. Each cell consists of a storage register, a second register and a multiplier. The storage register stores the data tap values, which are digital samples of the signal being processed by the filter. The second register stores the filter coefficients for a particular tap and the multiplier generates the product of the two register contents. The latter product serves as the output of the cell, and the weighted sum that constitutes the FIR filter output is generated by adding the outputs of all of the cells.