Low Power Layout Design of Priority Encoder Using 65nm Technology

Provided by: International Journal of Engineering Trends and Technology
Topic: Hardware
Format: PDF
In this paper, the authors provide comparative performance analysis of power and area of 4-bit priority encoder using 65nm technology. Two priority encoder approaches are presented, one with semi-custom and the other with full custom. The main objective is to compare semi-custom and full custom designed layout on the basis of two parameters which is power and area. Both the semi-custom circuit simulation and full custom has been done by manually layout created. Creation of layout in both types of method is done at 65nm CMOS technology.

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