Low Power Level-Up Shifter for Reduction of Static Power Dissipation in CMOS Technology
Static power dissipation is increases with the scaling in threshold voltage and expected to become important part of total power consumption. In the present work, a new configuration of level shifters for low power application in 0.25?m technology has been presented. The proposed circuits utilize the merit of stacking technique by which there is reduction in leakage power. In this paper, a new level-up shifter designed at ultra low core voltage and has wide range of I/O voltage. The circuit is designed using 0.25?m CMOS process.