Low Power Phase Locked Loop Design with Minimum Jitter

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Provided by: The International Journal of Innovative Research in Computer and Communication Engineering
Topic: Hardware
Format: PDF
In this paper, the authors describe a design of phase locked loop system with low power and minimum jitter. PLLs (Phase Locked Loops) with high speed, low noise and wide bandwidth with fast acquisition time are preferred. A PFD (Phase Frequency Detector) with low dead zone, charge pump with passive low pass filter and a low noise, wide tuning VCO (Voltage Controlled Oscillator) are integrated in the PLL system. A telescopic OTA based VCO with wide tuning range of 450MHz to 1.9GHz and power consumption of 0.30mW is designed. The PFD modeled is using 15 transistors and conventional charge pump with second order loop filter is used. Integrating this VCO in a PLL system offers low jitter and wide bandwidth.
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