Low-Power Pipelined Realization of Adaptive Filter Based on Distributed Arithmetic

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Provided by: International Journals of Advanced Information Science and Technology (IJAIST)
Topic: Hardware
Format: PDF
The major issues while designing a Distributed Arithmetic (DA) based adaptive filter are high power and area delay. In general speed and power are the essential factor in VLSI design. So, the authors have designing a new pipelined architecture for efficient Distributed Arithmetic (DA) based on LMS adaptive FIR filter. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations.
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