Applications of Engineering Technology and Science (AETS)
Testing of VLSI chips and power consumption is a challenging issue so the authors proposed the low power quasi-cyclic approach based test pattern generation scheme for further power reduction. A Test Pattern Generator (TPG) is used for generating different test patterns in Built-In Self-Test (BIST) schemes. This paper generates Multiple Single Input Change (MSIC) vectors in a pattern, applies each vector to a scan chain is a Single Input Change (SIC) vector. A MSIC-TPG and accumulator based TPG are designed and developed a reconfigurable Johnson Counter (JC) and a scalable SIC counter to generate a class of minimum transition sequences.