Low Power Reduced Router NoC Architecture Design With Classical Bus Based System
Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing communication requirements in digital systems. Network-on-Chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many-core systems. A novel switching mechanism, called virtual circuit switching, is implemented with circuit switching and packet switching. A path allocation algorithm is used to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized.
Subscribe to the Innovation Insider Newsletter
Catch up on the latest tech innovations that are changing the world, including IoT, 5G, the latest about phones, security, smart cities, AI, robotics, and more. Delivered Tuesdays and Fridays