In this paper, the efficient implementation of a pipeline FFT processor is presented. The design adopts a single path delay feedback as the proposed architecture. The Single-path Delay Feedback (SDF) pipeline requires less memory space and its multiplication utilization is less. Such implementations are advantageous to low power design, especially in portable DSP devices. Read only memories are used to store twiddle factors. In order to achieve a ROM less FFT processor, the proposed architecture uses a reconfigurable complex multiplier and bit parallel multiplier, and using the symmetry property of twiddle factors, low power is achieved.