Low Power Semiconductor Devices at 65nm Technology Node

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Topic: Hardware
Format: PDF
In this paper, the authors attempt to analyze the performance of 65 nm CMOS device structures for low power applications. It indicates that the historical trend of scaling of MOS devices can be sustained by innovative CMOS Structures such as Ultrathin body SOI devices and multiple gate MOSFETS (such as FinFETS), that can withstand the adverse effects of Scaling. A particular issue of great concern in logic design is the power dissipation. For high-performance logic with increased leakage currents, chip static power dissipation is expected to become a bottleneck to meet aggressive targets for performance scaling.
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