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SRAM memory is an essential building block for almost all processors and VLSI (Very Large Scale Integration) systems which have data storage and data transfer capabilities. It also accounts for large space in VLSI circuits and has major share in the power consumption of Integrated Circuits (IC). This paper presents a new 7T asymmetric SRAM cell, to address reduction in total power consumption and leakage power reduction in asymmetric 5T SRAM cell, during active mode of operation. The existing 5T SRAM has lesser total power consumption as compared to 6T SRAM cell, but has higher static power consumption.