Low Power State Retention Technique for CMOS VLSI Design
Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits as the battery leaks even when devices are in idle state. To reduce leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called Low Power State Retention technique (LPSR) is proposed in this paper. Earlier, well-known techniques for leakage reduction and state retention are compared with this paper.
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