Low Power Testing Techniques for Ultra Power Based SoC System

Provided by: World Academic Industry Research Collaboration Organization (WAIRCO)
Topic: Hardware
Format: PDF
To find the proper solutions for test power reduction strategy for parallel core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the efforts to reduce the power consumption during normal function mode further exaggerated the power consumption problem during test. The state-of-the-art in low-power testing is presented, various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test (BIST) techniques and the advances in LFSR techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed.

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