Low Power VLSI Circuit Design with Efficient HDL Coding

In this paper, four-bit unsigned up counter with an asynchronous clear and a clock enable is designed in Xilinx ISE 14.2 and implemented on high performance Virtex-6 FPGA, XC6VLX240T device, -1 speed grade, FFG1156 package and ML605 board. User Constraints File (UCF) and Net list Constraints Design (NCD) file are taken into consideration with XPower 14.2 for power consumption analysis. The authors take two codes. Their first code maps the clock enable signal to LUTs then the power consumption is 3.423 Watt.

Provided by: Institute of Electrical & Electronic Engineers Topic: Hardware Date Added: Aug 2013 Format: PDF

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