MAC Implementation Using Vedic Multiplication Algorithm
A conventional MAC unit consists of multiplier and an accumulator that contains the sum of the previous consecutive products. The paper presents the implementation of MAC (Multiplier-and-ACcumulator) unit using Vedic multiplier. The speed of MAC depends on the speed of the multiplier. The Vedic multiplier uses "Urdhva Tryagbhyam" algorithm. The proposed MAC unit is coded in VHDL, synthesized and simulated using Xilinx ISE 10.1 software. The MAC is implemented on a FPGA device XC2S200-6PQ208 using Xilinx ISE10.1 tool.