Provided by: International Association of Engineering and Management Education (IAEME)
Date Added: Sep 2012
In this paper, the authors propose the design of an adder circuit based on majority function. The adder comprises of only six MOS transistors. To make the design to be used invariably in the system with least nano device dimensions, some modifications have been done in the existing adder design. Post layout simulation result at 45nm TSMC technology confirms that the proposed design works faithfully in sub-threshold regime with appreciable 7 % of area reduction and 23.54% power saving with respect to earlier design.