Mapping DSP Applications on Processor Systems with Coarse-Grain Reconfigurable Hardware

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
In this paper, the authors present performance results from mapping five real-world DSP applications on an embedded System-on-Chip (SoC) that incorporates coarse-grain reconfigurable logic with an instruction-set processor. The reconfigurable logic is realized by a 2-dimensional array of processing elements. A mapping flow for improving application's performance by accelerating critical software parts, called kernels, on the coarse-grain reconfigurable array is proposed. Profiling is performed for detecting critical kernel code. For mapping the detected kernels on the reconfigurable logic a priority-based mapping algorithm has been developed.
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