MEDEA: A Hybrid Shared-Memory/Message-Passing Multiprocessor NoC-Based Architecture

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Provided by: edaa
Topic: Hardware
Format: PDF
The shared-memory model has been adopted, both for data exchange as well as synchronization using semaphores in almost every on-chip multiprocessor implementation, ranging from general purpose Chip Multi-Processors (CMPs) to domain specific multi-core Graphics Processing Units (GPUs). Low-latency synchronization is desirable but is hard to achieve in practice due to the memory hierarchy. On the contrary, an explicit exchange of synchronization tokens among the processing elements through dedicated on-chip links would be beneficial for the overall system performance.
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