Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures

Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, the authors propose a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A novel configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.