Memory Test Experiment: Industrial Results and Data

The results of 12 well-known and three fault-primitive-based memory test algorithms applied to 0.13 micron technology 512 kB single-port SRAMs are presented. Each test algorithm is used with up to 16 different Stress Combinations (SCs) (i.e. different address sequences, data backgrounds and voltages) resulting in 122 tests. The results show that SCs influence the Fault Coverage (FC) of the test algorithms, that the highest FC is obtained at a low voltage level and that the highest detected number of unique faults is obtained at a high voltage level.

Provided by: IEE Topic: Data Centers Date Added: Jan 2006 Format: PDF

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