Memory Testing with a RISC Microcontroller

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Provided by: edaa
Topic: Hardware
Format: PDF
Many systems are microcontroller based. Applications demand for production and power-on testing, which includes the memories. Because low-end microcontrollers typically do not have BIST, the CPU has to apply at least the Power-On tests. Considering the limited amount on-die memory, these tests have to be compact, while the test time should be short and the fault coverage high. Current technology typically has many long and thin wires with many interconnections (vias), such that speed related faults are a major concern. The way to detect speed related faults is by performing memory tests at-speed, using Back-to-Back (BtB) memory cycles.
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