Memristor-Based Multithreading

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Switch on Event Multi-Threading (SoE MT, also known as coarse-grained MT and block MT) processors run multiple threads on a pipeline machine, while the pipeline switches threads on stall events (e.g., cache miss). The thread switch penalty is determined by the number of stages in the pipeline that are flushed of in-flight instructions. In this paper, Continuous Flow Multi-Threading (CFMT), a new architecture of SoE MT, is introduced. In CFMT, a Multistate Pipeline Register (MPR) holds the microarchitectural state of multiple different threads within the execution pipeline stages, where only one thread is active at a time.

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