Metastability in CMOS Transmission Gate Base Interface Circuits

Provided by: International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE)
Topic: Hardware
Format: PDF
The authors' paper proposed metastability measurement system in which asynchronous data input and sampling clock frequencies trigger metastability, they demonstrate that dynamic memory cells present an anomalous behavior referred to as metastable operation with characteristics similar to those of static latches. During every cycle, the relative time of the two signals changes a bit, and eventually they switch sufficiently close to each other, leading to metastability. One common way to demonstrate metastability is to supply two clocks that differ very slightly in frequency to the data and clock inputs.

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