The University of Tulsa
In this paper, the authors present a preliminary evaluation of novel techniques that address a growing problem - power dissipation in on-chip interconnects. Recent studies have shown that around 50% of the dynamic power consumption in modern processors is within on-chip interconnects. The contribution of interconnect power to total chip power is expected to be higher in future communication-bound billion-transistor architectures. In this paper, they propose the design of a heterogeneous interconnect, where some wires are optimized for low latency and others are optimized for low power.