Minimally Buffered Router Using Weighted Deflection Routing for Mesh Network on Chip

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Provided by: Academy & Industry Research Collaboration Center
Topic: Networking
Format: PDF
The scalability, modularity and massive parallelism exhibited by Network-on-Chip (NoC) interconnects make them highly suitable for the inter core communication framework of Multi-Processor System-on-Chip (MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers. The advantages of buffer less and buffered designs can be combined by using a minimum number of side buffers to store a fraction of deflection flits in the router.
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