Journal of Semiconductor Technology and Science (JSTS)
Scaling down of transistors has resulted in dramatic increase of leakage current. Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, the authors focus on technology mapping, this is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit.