Minimizing Power Consumption in CMOS Full Subtractor Using SVL Technique

Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
Full subtractor using Self-controllable Voltage Level (SVL) technique is designed in this paper. The circuit can supply an increased DC voltage to an active load circuit required or can decrease the DC voltage supplied to a load circuit under standby mode is developed. Full subtractor is a consumed low power and low leakage as compare to conventional design with SVL technique. The authors may reduce the value of total power dissipation by applying the upper-SVL technology in which the supply potential is increased and lower-SVL technology in which the ground potential is raised.

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