Mitigating the Effects of Process Variations: Architectural Approaches for Improving Batch Performance

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Provided by: Northwestern University
Topic: Data Centers
Format: PDF
As transistor feature sizes continue to shrink into the sub-90nm range and beyond, the effects of process variations on critical path delay have amplified. A common concept to remedy the effects of variation is speed-binning, by which chips from a single batch are rated by a discrete range of frequencies. In this paper, the authors argue that under these conditions, architectural optimizations should consider their effect on the \"Batch\" of microprocessors rather than aiming at increasing the performance of a single processor.
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