Mixed Gates: Leakage Reduction Techniques Applied to Switches for On-Chip Networks

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Provided by: University of Rome
Topic: Hardware
Format: PDF
The reduction of power dissipation is a primary concern of current research in the field of integrated circuits. However, the user demand for high mobility and long operation time, especially of battery-operated devices, is contrary to the demand for high performance. Both demands could be satisfied for decades by aggressive downscaling of technology parameters. Thereby, the capacitive load per logic gate could be reduced which has allowed ever higher performance as well as decreased dynamic power consumption. Unfortunately, the influence of short channel and tunneling effects has increased exponentially which has resulted in dramatically increased leakage currents.
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