MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance
Several techniques aiming to improve power-efficiency (measured as EDP) in out-of-order cores trade energy with performance. Prime examples are the techniques to resize the Instruction Queue (IQ). While most of them produce good results, they fail to take into account that changing the timing of memory accesses can have significant consequences on the Memory-Level Parallelism (MLP) of the application and thus incur disproportional performance degradation. The authors propose a novel mechanism that deals with this realization by collecting fine-grain information about the maximum IQ resizing that does not affect the MLP of the program.