Model-Based Representation of Schedules for Dataflow Graphs

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Provided by: University of Engineering and Technology, Taxila
Topic: Hardware
Format: PDF
Dataflow models of computation are often used in model-based MPSoC design flows, as they naturally expose the parallelism contained in an application. In a dataflow model, concurrent processes communicate via packets transmitted over channels. During system design, actors mapped to the same processing element must be scheduled. While model-based schedule representations are desirable, existing approaches are either restricted to static dataflow models for which static schedules can be determined, or they introduce special scheduling actors with different semantics compared to actors of the underlying dataflow model, thereby hampering hierarchical composition.
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