Modeling and Mitigating Transient Errors in Logic Circuits
Transient or soft errors caused by various environmental effects are a growing concern in micro and nano-electronics. The authors present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. They observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is non-critical at the system level, they define the Critical Soft Error Rate (CSER) as a more realistic alternative to the conventional SER measure.