Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors

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Provided by: CNRS
Topic: Hardware
Format: PDF
The authors introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-on-chips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, their results can be used, for instance by engineers designing power or thermal management units, to cancel the temperature induced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instances of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior.
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