Modelling and Testing of Gate Oxide Shorts in SRAM and DRAM

Provided by: Creative Commons
Topic: Hardware
Format: PDF
Gate oxide shorts have become a dominant failure in MOSFET while designing an IC. This defect will surely affect the yield and reliability of the device and memory. Therefore, a GOS model that represent the minimum size GOS impacted MOSFET is introduced. First, a 6T SRAM (Static Random Access Memory) cell structure is designed and the MOSFET having this defect in SRAM is detected by a test method which results in malfunction of the memory operation.

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