Modified 4-Bit Comparator Using Sleep Technique
The development of digital integrated circuits is challenged by higher power consumption. So low power circuits have become a top priority in modern VLSI design. This paper presents layout simulations of a new improved four bit comparator design. The proposed design demonstrates its superiority against existing four bit comparator design in terms of power consumption. The proposed comparator has been designed using micro-wind. The developed comparator shows 42.18% improvement in power when compared to the existing method.