Provided by: International Journal of Engineering, Science and Innovative Technology (IJESIT)
Date Added: Sep 2014
A new low area-cost FIR filter design is proposed using a modified Booth multiplier based on direct form realization. Verilog is used as HDL. Implementation is done in ModelSim SE 6.5 and Xilinx Spartan II FPGA. FIR filters using faithfully rounded MCMAT and an older version truncated multiplier are also implemented for comparison with the previously existing systems. Most prior designs are based on transposed form. But, the results show that the proposed design using direct form is more area-efficient when compared with the conventional FIR filter designs. Power consumption and delay time can also be reduced.