International Journal of Computer Applications
The use of adiabatic Logic in VLSI chip design has certainly promised positive aspects in terms of optimizing the power equations. In the reported paper, authors have extended their proposed CPLAG based 'XOR' implementation. The modified 'XOR' implementation is further configured to implement a dynamic positive edge triggered D flip-flop. Both the reported circuits are functionally verified and found to be satisfactory to a high degree of signal integrity and accuracy. DFF circuit is further examined with different load, temperature range, and transistors size and voltage levels.