Modified FSM Based 32-Bit Unsigned High Speed Pipelined Multiplier Using Carry Look Ahead Adders In Verilog HDL
In many digital system designs multiplier unit is the main block. This paper shows a modification to FSM based 32-bit unsigned pipelined multiplier. It uses Carry Look ahead Adders (CLA's) in place of Ripple Carry Adders (RCA's) in 32-bit FSM based pipelined multiplier. Proposed multiplier design uses only 1179 slices and 2006 4 input LUT's. Synthesis report shows that modified FSM based 32-bit unsigned pipelined multiplier has less delay, less usage of logical resources, than FSM based pipelined multiplier. Simulation was done in Xilinx ISE 13.2 (Verilog HDL).