Pontifical Catholic University of Rio de Janeiro
In this paper, the authors describe a scalable and reusable architecture useful for the construction of Ethernet switches, named MOTIM. The main requirement of MOTIM is to allow achieving low latency and high throughput with a generic structure that can be easily scaled. In order to make the architecture scalable, its design is based on the use of a Network-on-Chip (NoC), a concept recently proposed for enhancing SoC interconnects design. NoCs stand as a good compromise between silicon cost and performance scalability, easing to attain design requirements. The researcher recently identified a set of trends arising in packet switch design and discussed their consequences.