Multi-Bit Error Tolerant Caches Using Two-Dimensional Error Coding

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
With the scaling of process technologies into the nanometer regime, the reliability of embedded memory systems becomes an increasingly important concern for digital system designers. Nanoscale components themselves are increasingly likely to fail, and the growing amount of on-chip memory creates more possible points of failure. As designers integrate more of the memory hierarchy onto the processing die, the number and size of memory arrays on these System-on-Chip (SoC) and microprocessors will increase. Therefore, errors occurring in the embedded memory systems are a growing threat to the overall SoC and processor reliability and yield.

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