Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors

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Provided by: Pennsylvania State Employees Credit Union
Topic: Hardware
Format: PDF
In this paper, the authors propose an Integer Linear Programming (ILP) solution to the combined problem of memory hierarchy design and data allocation in the context of embedded chip multiprocessors. The proposed solution uses compiler analysis to extract data access patterns of parallel processors and employs integer linear programming for determining optimal on-chip memory partitioning across processors and data allocations across the resulting memory components. Their experimental results show that the application specific on-chip memory hierarchies designed using this approach are much more energy efficient than conventional on-chip memories, conventional caches, and those designed by a prior work that partitions memory space across parallel processors without designing a multi-level hierarchy.
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