Multi-Level Power Consumption Modelling in the AADL Design Flow for DSP, GPP, and FPGA

Provided by: RWTH Aachen University
Topic: Hardware
Format: PDF
In this paper, the authors present a method that permits to estimate the power consumption of components in the AADL (Architecture Analysis & Design Language) component assembly model, once deployed onto components in the AADL target platform model. This estimation is performed at different levels in the AADL refinement process. Multi-level power models have been specifically developed for the different type of possible hardware targets: General Purpose Processors (GPPs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs).

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