Université Paris Diderot
Optical Network-on-Chip (ONoC) architectures are emerging as promising contenders to solve bandwidth and latency issues in Multi-Processor Systems-on-Chip (MPSoC). However, current on-chip integration technologies for optical interconnect allow interconnecting only dozens of IPs. Scaling with MPSoCs composed of hundreds of IPs thus, relies on unpredictable technological innovations. In this paper, the authors propose a method that combines multiple ONoCs. Each ONoC is small enough to rely on already existing and proven technologies. They evaluate the approach for various interconnect scenarios, showing that it scales well with the size of the MPSoC architectures.