International Journal of Engineering Trends and Technology
In this paper, the author's design of an asynchronous FPGA blocks is implemented with power optimization techniques. Concentrated on standby and dynamic power consumptions are presented and studied on various gating techniques. The existing techniques are standby power is reduced by using autonomous fine grain power gating and reducing the dynamic power by using the Level Encoding Dual Rail (LEDR) architecture. The proposed present circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption in look up table in FPGA.