Multi Retention Level STT-RAM Cache Designs with a Dynamic Refresh Scheme

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Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
Spin-Transfer Torque Random Access Memory (STT-RAM) has received increasing attention because of its attractive features: good scalability, zero standby power and non-volatility and radiation hardness. The use of STT-RAM technology in the last level on-chip caches has been proposed as it minimizes cache leakage power with technology scaling down. Furthermore, the cell area of STT-RAM is only 1=9 and 1=3 that of SRAM. This allows for a much larger cache with the same die footprint, improving overall system performance through reducing cache misses.
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