Multioperand Redundant Compressor Trees on FPGAs
Multi-operand adders, which found in parallel multipliers, they consist of the compression trees i.e. 9:2, 11:2, 15:2 and 32:2. In this paper, redundant adders were used to design parallel multi-operand adders for ASIC implementations. The use of redundant adders on Field Programmable Gate Arrays (FPGAs) has been avoided because implementation of Carry Propagate Adders (CPAs) and the area overhead of the redundant adders is very high; delay is more because 'n' numbers of adders are connected.